What in Electronics?
FPGA
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3:58
9
- 1 What is an FPGA (Field Programmable Gate Array)? | FPGA Concepts 3:58
- 2 How to Get Started With FPGA Programming? | 5 Tips for Beginners 8:21
- 3 FPGA Programming Projects for Beginners | FPGA Concepts 4:43
- 4 How to Download And Install Xilinx Vivado Design Suite? | Xilinx FPGA Programming Tutorials 2:29
- 5 How To Create First Xilinx FPGA Project? | Xilinx FPGA Programming Tutorials 11:21
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15:21
12
- 1 Introduction to FPGA Part 1 – What is an FPGA? | Digi-Key Electronics 15:21
- 2 Introduction to FPGA Part 2 – Getting Started with Yosys, IceStorm, and Apio | Digi-Key Electronics 18:51
- 3 Introduction to FPGA Part 3 – Getting Started with Verilog | Digi-Key Electronics 20:44
- 4 Introduction to FPGA Part 4 – Clocks and Procedural Assignments | Digi-Key Electronics 18:09
- 5 Introduction to FPGA Part 5 – Finite State Machines | Digi-Key Electronics 24:24
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37:44
84
- 1 EEVblog #496 – What Is An FPGA? 37:44
- 2 Altera Quartus II Tutorial v11.1 10:48
- 3 What is an FPGA? Intro for Beginners 13:22
- 4 Hello World on your FPGA 18:33
- 5 Using Simulink to Deploy a MATLAB Algorithm on an FPGA or ASIC 8:19
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30:53
25
- 1 VHDL Lecture 1 VHDL Basics 30:53
- 2 VHDL Lecture 2 Understanding Entity, Bit, Std logic and data modes 14:33
- 3 VHDL Lecture 3 Lab1 Switches LEDs Explanation 13:25
- 4 VHDL Lecture 4 Lab1-Switches LEDs Simulation 9:53
- 5 VHDL Lecture 5 Understanding Architecture 15:30
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40:37
41
- 1 Introduction to Verilog: Modules, Number Representations & Comments | Free DV Course|All about VLSI 40:37
- 2 Verilog Data Types Explained | reg, net, integer, real, time | Verilog Tutorial for Beginners 49:06
- 3 Port Connection Rules in Verilog | Connect by Order vs Connect by Name Explained 46:45
- 4 Introduction to Gate Level Modeling in Verilog | Getting Started with Vivado Tool Interface 31:36
- 5 Verilog Code for Full Adder using Half Adder | Gate Level Modeling | All about VLSI || 19:15
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23:59
19
- 1 Easy Tutorial on FPGA Coding by Using Vivado, Verilog, and Xilinx Boards 23:59
- 2 Transform Integers Into Binary Numbers in C/C++ and Bitwise Operations – Tutorial 22:08
- 3 Install MicroBlaze Processor and Start with C/C++ Coding FPGAs in Vivado and Vitis 19:17
- 4 Pulse Width Modulation (PWM) in FPGA, Verilog, and Vivado – Make External Breadboard LED Blink 25:57
- 5 Fix the Vivado error: Cannot locate target loader vivado.bat – C:XilinxVivado…vivado.bat 3:18
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2:28
38
- 1 VHDL Programming – Course Announcement 2:28
- 2 Introduction to VHDL Programming 12:06
- 3 VHDL Fundamentals 10:58
- 4 History of VHDL 6:19
- 5 Digital Design Flow 11:19
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26:45
17
- 1 Day 1 | Full Adder Dataflow (DF) RTL Code & Testbench | Vivado, Quartus & ModelSim Simulation 26:45
- 2 Day 2 of 30 Days of Verilog HDL | Ripple Carry Adder (RCA) RTL Code & Testbench 29:05
- 3 Day 3 of 30 Days of Verilog HDL | Binary to Gray and Gray to Binary Converter RTL code and Testbench 31:51
- 4 Day 4 of 30 Days of Verilog HDL | 2×1 MUX RTL Code and Testbench 12:18
- 5 Day 4 of 30 Days of Verilog HDL | 4×1 MUX and 8×1 MUX RTL Code & Testbench 21:20