Save Data to Files from Verilog and Vivado Simulations – FPGA Tutorial

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– In this FPGA, Verilog, and Vivado tutorial, we explain how to save simulation data to files from Verilog and Vivado simulations.

Motivation: The standard practice when developing and implementing FPGA algorithms is to first implement and test algorithms in MATLAB and Python. This is done since it is significantly easier to test algorithms in MATLAB or Python than in FPGAs. After MATLAB or Python simulation confirm that algorithms work as expected, the next stage is to implement them in Verilog and to simulate them in the Vivado development environment. The final stage is the FPGA implementation. During testing and simulation in Verilog and Vivado, it is often necessary to save simulation data to files such that the Verilog simulation data can be compared with data generated in Python and MATLAB. Consequently, we need to know how to save Verilog simulation data to files.

That is, the material presented in this tutorial is very important for developing and simulating algorithms in Verilog.

Outline:
We will first write the Verilog module.
Then, we will write a Verilog simulation file (test bench file). The Verilog simulation will first load test data from a file. The test data is a two-bit binary sequence that is inverted by the Verilog module.
Then, we will save the inverted sequence to another data file.