Introduction to FPGA Part 7 – Verilog Testbenches and Simulation | Digi-Key Electronics

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to create modules in Verilog and use parameters to change the functionality of instantiated modules (https://youtu.be/0BKyiY8R5NU). We’ll build on those concepts in this video, where we demonstrate how to create a testbench in Verilog, simulate the design with Icarus Verilog (iverilog), and view the output waveform with GTKWave.

The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-7-verilog-testbenches-and-simulation/1b741d1b8b864afeacbe28075b1427cd

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

Uploading your design to a real FPGA can sometimes take a while (especially for larger designs and denser FPGAs). Additionally, to check the timing and operation for fast-changing signals (think RAM bus or USB signals), you would need other specialized test equipment, such as a logic analyzer. Connecting all of the FPGA pins to a logic analyzer can also be a time-consuming processor.

To save us time, we can write Verilog code that tests our design (known as a “testbench”). We use a special simulation program (Icarus Verilog, in our case) to run the testbench code. The testbench code should instantiate the module(s) under test (often called a “unit under test” or “uut”) and toggle the necessary input lines.

The simulation will run our testbench, and it will log all how and when the various signals/wires change in the design. It will store this log in a “value change dumpfile” (.vcd). We can use a waveform viewer, such as GTKWave, to visualize these changes. The waveforms should look similar to what you might find on a logic analyzer.

Your challenge is to create a Verilog testbench for your button debouncing code from episode 5. You are welcome to use my solution to that challenge as a starting point (https://github.com/ShawnHymel/introduction-to-fpga/tree/main/05-finite-state-machines/solution-button-debouncing). Note that you might need to make some changes to the original code to allow for passing parameters to the design.

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88

Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-7-verilog-testbenches-and-simulation/1b741d1b8b864afeacbe28075b1427cd

Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

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