Introduction to FPGA Part 10 – Metastability and Clock Domain Crossing | Digi-Key Electronics

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

Previously, we showed how to use a phase-locked loop (PLL) to increase clock speed as well as introduced the concept of glitches. In this episode, we examine how setup and hold time violations can cause metastability in flip-flops.

The solution to the challenge at the end of the episode can be found here: https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-10-metastability-and-fifo/74884ed134474e008a1e444ea9dacb0f

All code examples and solutions for this series can be found here: https://github.com/ShawnHymel/introduction-to-fpga

Colin O’Flynn’s metastability experiment: https://colinoflynn.com/2020/12/experimenting-with-metastability-and-multiple-clocks-on-fpgas

Better clock divider example: https://github.com/ShawnHymel/introduction-to-fpga/tree/main/10-metastability/example-02-better-clock-divider

Better button debounce design: https://github.com/ShawnHymel/introduction-to-fpga/tree/main/10-metastability/example-03-better-debouncer

Clifford Cummings’s FIFO paper: http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf

A flip-flop requires the input signal to be steady for some time before the clock edge (setup time) and remain steady for some time after the clock edge (hold time). If the input signal transitions during the setup or hold windows, then it is considered a timing violation. This could potentially cause metastability on the flip-flop, where the output remains in an unknown state for some indeterminate amount of time.

Normally, the metastable output will settle on logic high or logic low quickly (within a few nanoseconds), but it is not guaranteed. Metastable events can cause potentially catastrophic failures in a design and can be very difficult to track down due to their probabilistic nature.

The standard fix to mitigate the likelihood and impact of metastability is to use a synchronizer circuit, which consists of 2 or more flip-flops chained together. The input of one flip-flop samples the output of another. Note that this introduces an extra clock cycle of delay for each flip-flop you put in the chain.

A first-in, first-out (FIFO) system is one way to pass data from one class domain to another. Elements are read from the FIFO in the order in which they were written. We can use dual-port block RAM to construct a FIFO in our iCE40. Your challenge is to implement Clifford Cummings’s FIFO design and test it via simulation.

Product Links:
https://www.digikey.com/en/products/detail/lattice-semiconductor-corporation/ICE40HX1K-STICK-EVN/4289604

Related Videos:
https://www.youtube.com/watch?v=z8Oldd-nrfs
https://www.youtube.com/watch?v=5kNXX67mchE
https://www.youtube.com/watch?v=iwcxLQ6AB88

Related Project Links:
https://www.digikey.com/en/maker/projects/introduction-to-fpga-part-10-metastability-and-fifo/74884ed134474e008a1e444ea9dacb0f

Related Articles:
https://www.digikey.com/en/pdf/r/renesas-electronics-america/powering-fpga-applications
https://www.digikey.com/en/videos/d/dsp/edge-machine-deep-learning-on-fpga

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