Day 10 of 30 Days of Verilog HDL | 4-bit Custom Comparator | RTL Code, Testbench & Simulation

Welcome to **Day 10** of the **30 Days of Verilog HDL** series!

In this video, you’ll learn how to design and verify a **4-bit Custom Comparator** using **Verilog HDL**. We will implement the RTL code, develop a comprehensive testbench, and simulate the design to verify the comparator outputs through waveform analysis.

### 📌 What You’ll Learn

* Introduction to 4-bit Custom Comparator
* Comparator logic and working principle
* RTL coding in Verilog HDL
* Writing a Verilog testbench
* Running simulation
* Waveform analysis and output verification
* Digital Design and RTL Design concepts

### 🛠 Tools Used

* Xilinx Vivado / Vivado Simulator
* ModelSim / QuestaSim (optional)
* Verilog HDL

### 🎯 Who Should Watch?

* VLSI Beginners
* ECE & EEE Students
* RTL Design Engineers
* FPGA Developers
* Interview Preparation Aspirants
* Anyone learning Verilog HDL and Digital Electronics

### 📚 30 Days of Verilog HDL Playlist

Follow the complete playlist to master Verilog HDL from basic to advanced concepts with hands-on coding examples.

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