Day 1 | Full Adder Dataflow (DF) RTL Code & Testbench | Vivado, Quartus & ModelSim Simulation

Welcome to Day 1 of the Digital Design & Verilog HDL Series.

In this video, we learn how to design a 1-Bit Full Adder using Dataflow Modeling (DF) in Verilog HDL. We will write the RTL code, develop a testbench, and simulate the design using Xilinx Vivado, Intel Quartus Prime, and ModelSim.

Topics Covered:

✅ Introduction to Full Adder
✅ Full Adder Truth Table
✅ Dataflow Modeling in Verilog HDL
✅ RTL Code Explanation
✅ Testbench Development
✅ Simulation in ModelSim
✅ Vivado Project Creation & Simulation
✅ Quartus Prime Compilation & Analysis
✅ Verification of Sum and Carry Outputs

Full Adder Equation:
Sum = A ⊕ B ⊕ Cin
Carry = (A & B) + (B & Cin) + (A & Cin)
What You Will Learn:
Verilog Dataflow Modeling
RTL Design Methodology
Testbench Writing Techniques
Digital Logic Design Fundamentals
Simulation and Verification Flow
FPGA Design Basics

This tutorial is ideal for ECE, EEE, EIE, CSE students, VLSI beginners, FPGA enthusiasts, and interview preparation.

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